The clocked storage element, a level sensitive latch or an edge triggered flip-flop, are used to partition nearly every pipeline stage of a modem microprocessor. Clocked storage elements are utilized in this manner because they hold the current state of a pipeline stage and prevent the next state from entering the pipeline stage until scheduled to do so. Consequently, the clocked storage element synchronizes events between concurrent logic elements with different operational delays. As such, the design of a clocked storage element is tightly coupled to the clocking strategy and circuit topology of the system architecture.
In synchronous sequential circuits, switching events in various stages of the pipeline take place concurrently in response to a clock stimulus. New sets of inputs to the pipeline stages are sampled by the clocked storage elements and new computations are produced that change the state of the sequential network. Once complete, the results of the computations await the next clock transition to advance to next pipeline stage. Hence, any deviation in the clock period affects cycle time and performance of the microprocessor. Moreover, deviation in the clock period can create race conditions that cause the next state of a pipeline stage to race into a clocked storage element and corrupt its current state.
Given the difficulty of globally distributing multiple wire non-overlapping clocks, the generation and distribution of a single wire global clock is the current trend in microprocessor design. As such, scan testing of electronic systems that combine edge triggered flip-flops and level sensitive latches on a two phase single wire clock presents several problems with respect to system clocking, scan test clocking and clock control. The current scan test systems that fall into two general categories. The first category is known as “MuxScan” and employs edge triggered storage elements with a multiplexer coupled to the inputs of the storage elements to select between non-scan data and scan data. The second category typically employs level sensitive scan design (LSSD) whereby a multiplexer is coupled to the input of the level sensitive storage device to select between non-scan data and scan data.
LSSD scan testing typically utilizes two separate clocks that are non-overlapping to clock scan data into level sensitive latches. In comparison, MuxScan testing utilizes one clock, the system clock, along with a scan enable control signal, since data is sampled on a clock edge. Unfortunately, both techniques include a scan select multiplexer in the data path of the clocked storage element that increases data latency through a pipeline stage, thereby reducing the performance characteristics of the electronic design.
In addition, the two scan techniques described above typically require their main system clock to stop while shifting scan data into and out of the scannable electronic assembly. Consequently, scan techniques, such as sequential scan testing at system clock speed, critical path testing of functional test vectors at full system clock speed is problematic because the system clock is not allowed to run without interruption. An additional shortcoming of the two conventional systems for performing scan testing is that each system is generally adapted for use with only one type of clocked storage element. For example, the MuxScan system is usually adapted for use with edge triggered flip-flops while the LSSD scan system is usually adapted for use with a level sensitive latch. Unfortunately, it is desirable to make use of both latches and flip-flops in the same system or data pipeline that are correspondingly driven via the same single wire clock to define the timing characteristics of a data pipeline.
Furthermore, the two traditional systems for scan testing level sensitive latches (LSSD) and edge triggered flip-flops (MuxScan) do not lend themselves for use with dynamic logic circuits. This is especially true when the system clock is required to stop during the scan chain shifting process. Unfortunately, a dynamic logic circuit is designed to evaluate via a self timed path driven from one edge of the system clock. This explains why in the two conventional scan systems of performing scan control and observation, the clock to the clocked storage element is typically halted prior to the scan cycle evaluation. Moreover, halting of the main system clock allows only dynamic circuits in one clock phase to evaluate correctly. This is because circuits in the opposite clock phase must be pre-charged prior to evaluation in order to produce the correct logic value. As such, the use of one or both of the conventional scan systems provides an undue burden to scan testing very large scale integration (VLSI) circuits, such as a microprocessor. Furthermore, halting of the system clock causes undesirable current transients on the power system of the VLSI design that can cause significant damage to current sensitive devices within the VLSI design.